Using ADF4007 high frequency divider PLL synthesizer can be designed a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider prescaler. The divider prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator).
This Local Oscillator electronic project use the ADF4007 with the HMC358MS8G VCO from Hittite Microwave Corporation to produce a fixed-frequency LO (local oscillator), which could be used in satellite or CATV applications. In this case, the desired LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω.
To bias the REFIN pin at AVDD/2, ac coupling is used. The value of the coupling capacitor used depends on the input frequency. The equivalent impedance at the input frequency should be less than 10 Ω. Given that the dc input impedance at the REFIN pin is 100 kΩ, less than 0.1% of the signal is lost.
The charge pump output of the ADF4007 drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system is 45°.Other PLL system specifications are as follows:
KD = 5 mA KV = 100 MHz/V Loop Bandwidth = 300 kHz FPFD = 106 MHz N = 64 .
The local oscillator circuit gives a typical phase noise performance of −100 dBc/Hz at 10 kHz offset from the carrier.
